The present invention relates generally to voltage slew rates in electronic circuits, and, more specifically, to a new circuit and method for dynamically adjusting the voltage slew rate of an electronic circuit.
Many electronic circuits include a voltage input, which can be supplied by various sources of electrical power. As a result of a dynamically-changing input voltage or as a result of various state changes in the electronic circuit, such as switches turning xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d, and changing input parameters to the circuit, the voltage levels at various points throughout the circuit change. However, while a change in input voltage or a change in a state of the electronic circuit is often accomplished according to a step function, such as a switch instantaneously changing from an xe2x80x9conxe2x80x9d state to an xe2x80x9coffxe2x80x9d state, or an input voltage changing instantaneously from a xe2x80x9chighxe2x80x9d voltage to a xe2x80x9clowxe2x80x9d voltage, the responding voltage levels throughout the electronic circuit tend not to change instantaneously. The inherent capacitance of most electronic components causes the change in voltage across such components to follow behind the input change. This delayed change in the responsive voltage level is referred to as a xe2x80x9cvoltage slew ratexe2x80x9d, and it is defined as the change in voltage level over time.
In the context of pulse-width modulation (PWM) circuits, the voltage slew rate of the circuit is known to affect two undesirable phenomena, specifically, electromagnetic interference (EMI) and power dissipation (switching losses), in opposite ways. These phenomena are of particular interest in a circuit wherein the electronic switches (transistors) change state many times, such as in a pulse-width modulated circuit. Specifically, low voltage slew rates (slow voltage change rates) result in relatively less EMI, but also lead to relatively more power dissipation. Conversely, high voltage slew rates (fast voltage change rates) result in relatively less power dissipation, but also lead to relatively higher levels of EMI. In conventional PWM circuits, the voltage slew rate is optimized for a preferred performance level. The voltage slew rate is adjusted to achieve either the best possible EMI performance while keeping switching losses within a given limit, or, alternatively, the slew rate is adjusted to achieve the smallest possible switching losses while maintaining the EMI level below a maximum value. The voltage slew rate is normally optimized by adjusting the size of various resistors and/or capacitors in the circuit, thereby adjusting the RC time constant, which dictates the length of the voltage slew rate. In a pulse width modulation circuit, the preferred RC time constant depends partially on the frequency of the input voltage to the circuit. For instance, at higher frequencies, the transistors in the circuit change state more often, which translates into a higher preferred slew rate to minimize power dissipation. Conversely, at lower frequencies, the transistors in the circuit change state less often, which translates into a lower preferred slew rate to minimize EMI (since, for lower frequency, larger switching losses are acceptable to keep the average power dissipation within a given limit).
By way of example, a known PWM circuit is shown in FIG. 1. An input voltage signal, PWM-IN, is provided, which causes an electrical current to flow through resistor Rg. The current flows into the gate of transistor Qmain, creating a voltage across the gate and the source which ultimately turns Qmain xe2x80x9conxe2x80x9d, thereby allowing electrical current to flow therethrough from a power source, xe2x80x9cPower In.xe2x80x9d PWM-IN varies between a xe2x80x9chighxe2x80x9d voltage and a xe2x80x9clowxe2x80x9d voltage, and, as a result, Qmain alternatively turns xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d and the electrical current from the xe2x80x9cPower Inxe2x80x9d source delivers an electrical pulse train to an output load (not shown). Equivalent capacitance Ciss, shown in dotted lines in FIG. 1, is not a physical component in the circuit, but, rather, represents the equivalent capacitance of transistor Qmain. As a result of the equivalent capacitance Ciss (which requires being charged), the voltage level at the gate of Qmain follows the PWM-IN voltage in a delayed manner. The amount of the delay, or xe2x80x9cslewxe2x80x9d, is determined by the RC time constant, xcfx84, which is mathematically determined according to the following: xcfx84=Rg*Ciss. Depending upon the frequency of the input voltage, PWM-IN, the RC time constant can be adjusted by adjusting the values of Rg and/or Ciss.
The above-described methodology of optimizing the voltage slew rate of a pulse modulation circuit works adequately when the frequency of the circuit is a constant. However, if the PWM circuit is intended to operate on a variety of frequencies, then the above-methodology is less desirable because the voltage slew rate must be designed to accommodate the highest possible frequency in the system. As a result, the system suffers either unnecessarily high EMI levels when the system is operated at relatively low frequencies, or the system must unnecessarily incorporate over-sized switching transistors (Qmain in FIG. 1) to accommodate the high power dissipation when the system is operated at relatively high frequencies. In either case, the system is not optimized.
Therefore, the inventors hereof have recognized the need for a new circuit and method for dynamically adjusting the voltage slew rate of an electronic circuit.
The present invention relates to a new circuit and method for adjusting the voltage slew rate of an electronic circuit. In particular, the inventive circuit includes a means for dynamically controlling the equivalent resistance of the electronic circuit. In one embodiment of the invention, the equivalent resistance of the circuit is adjusted in response to at least one control signal.